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beneits and features g3-plc? compliant prestandard conformance: ieee ? p1901.2, itu g.9903 frequency-band compliant with cenelec, fcc, and arib operating frequency from 10khz to 490khz single-chip solution integrating physical layer (phy) and media access controller (mac) two uart and two spi? interfaces supports ipv6-compatible networking layer ? 6lowpan ipv6 header compression maximizes payload size ? dynamic routing mechanism supports mesh networking ? csma/ca (carrier sense multiple access with collision avoidance/channel access) high-speed, reliable communication ? data rate of up to 300kbps ? two layers of forward error correction (fec) and cyclic redundancy check (crc16) ? enhanced fec with reed-solomon and viterbi ? ccm* authentication coprocessor featuring aes-128 encryption/decryption ? automatic repeat request (arq) enhances error detection and data reliability ? dynamic link adaptation to select optimum data rate based on channel condition ? programmable tone notching aec-q100 automotive qualified applications smart grid communications advanced metering infrastructure (ami) smart meters ami concentrators electronic vehicle charging street lighting automation home energy monitoring building automation solar and renewable energy management general description the max2992 powerline communication (plc) baseband modem delivers half-duplex, asynchronous data commu - nication over ac power lines at speeds up to 300kbps (full fcc band data rate). the max2992 is a system-on-chip (soc) that combines the physical (phy) and media access control (mac) layers using maxims 32-bit maxq30 micro - controller core. the max2991 integrated analog front-end transceiver interfaces seamlessly with the max2992, and together with the max2992 g3-plc firmware, forms a complete g3-plc-compliant modem solution. the max2992 utilizes ofdm techniques with dbpsk, dqpsk, d8psk modulation and forward error correc - tion (fec) to enable robust data communication using the electrical power grid. the design provides inherent adaptability to frequency selective channels, robustness in the presence of group delay, and immunity to impulsive noise. to allow for regulatory compliance, the max2992 incorporates a programmable tone notching mechanism. this allows the notching of certain frequency bands in the transmit spectrum of the modem. this feature also pro - vides an alternative method to address coexistence with other narrowband transmitters such as legacy fsk-based plc systems. the max2992 mac incorporates a 6lowpan adaptation layer to support ipv6 packets. an enhanced csma/ca and arq, together with the mesh routing protocol, sup - ports all common mac layer services for various network topologies. intelligent communication mechanisms adapt and enhance system performance over a range of channel conditions. these mechanisms include channel estimation, adaptive tone mapping, and routing protocols. an on-chip ccm (an extension of ccm specified in ieee 802.15.4) authentication coprocessor with aes-128 encryption/ decryption provides security and authentication. ordering information continued at end of data sheet. g3-plc is a trademark of maxim integrated products, inc. spi is a trademark of motorola, inc. ieee is registered service mark of the institute of electrical and electronics engineers, inc. 19-5812; rev 1; 4/14 + denotes lead(pb)-free/rohs-compliant package. part temp range pin-package max2992ecb+ -40c to +85c 64 lqfp max2992 g3-plc mac/phy powerline transceiver ordering information downloaded from: http:///
max2992 max2991 host application c interface mcu tx block rx block afe line driver line coupler flash (g3-plc firmware) ac powerline phy max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 2 typical application circuit downloaded from: http:///
table of contents benefits and features .......................................................................... 1 applications .................................................................................. 1 general description ............................................................................ 1 device details ................................................................................ 5 functional diagram ................................................... ........................ 5 pin configuration ................................................... ......................... 6 pin description ................................................... ........................... 7 typical operating characteristics ................................................... ............ 13 detailed description ................................................... ...................... 13 power management ................................................... .................... 13 normal operating mode ................................................... ............... 13 idle mode ................................................... .......................... 13 stop mode .................................................. .......................... 13 uart interface ................................................... ....................... 14 serial peripheral interface (spi) ................................................... .......... 14 gpio ................................................... ............................... 14 timers ................................................... .............................. 14 clocks, pll, and power-on-reset ................................................... ......... 14 external reset ................................................... ........................ 15 watchdog timer ................................................... ....................... 15 afe serial interface ................................................... .................... 15 boot options ................................................... ......................... 15 automatic bootstrap from flash ................................................... ......... 15 bootstrap using the uart0 loader ................................................... ...... 15 bootstrap using the jtag loader .................................................. ........ 17 ac phase detector ................................................... .................... 17 csma/ca ................................................... ............................ 17 automatic repeat request (arq) ................................................... ......... 17 phy overview .................................................. ......................... 17 electrical characteristics ....................................................................... 20 absolute maximum ratings ................................................... ................ 20 package thermal characteristics ................................................... ............ 20 electrical characteristics table ................................................... .............. 20 ac electrical characteristics ................................................... ............... 21 applications information ................................................... ................... 24 external crystal requirements .................................................. ............ 24 external flash requirements ................................................... ............ 24 max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 3 downloaded from: http:///
list of figures list of tables table of contents (continued) figure 1. gpio ............................................................................... 14 figure 2 . max2992 to max2991 interface ......................................................... 15 figure 3. max2992 boot sequence flow chart ..................................................... 16 figure 4. zero-crossing ac detector ............................................................. 17 figure 5. transmitter/receiver block diagram of the baseband processor ................................ 19 figure 6. spi master timing diagram ............................................................. 23 figure 7. spi slave timing diagram .............................................................. 23 figure 8. afe timing diagram .................................................................. 24 figure 9. star network topology ................................................................. 25 figure 10. tree network topology ................................................................ 25 figure 11. peer-to-peer network topology ......................................................... 25 figure 12. route request message flow .......................................................... 26 figure 13. route reply message flow ............................................................ 26 table 1. frequency bands supported by the max2992 ............................................... 18 table 2. frame error rate requirements in awgn channels (100 b ytes) ................................ 18 table 3. receiver specification with max2991 ...................................................... 18 network support ................................................... ...................... 25 max2992 routing .................................................. .................... 25 chip information .............................................................................. 27 package information .......................................................................... 27 revision history .............................................................................. 28 max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 4 downloaded from: http:///
clock domain boundary phy rx path deinterleaver veterbi decoder reed solomon descrambler sync detector fft demodulator channel estimator phy tx path interleaver convolution encoder reed solomon scrambler modulation mapper mult m plls plls1plls2 xtals xtal1s xtal2s div n div o afe interface data memory data line interrupt control watch dog spi0 (boot loader) serial flash rxconv enrx rxdata rxclk txconv entx txdata txclk afe_ rst fsh_sck fsh_so fsh_si fsh_cs xtals clk_cpu clk_phy plls1 plls2 plla2 tck tms tdi tdo rst multiplier uart1 uart0 (boot loader) spi1 aes ccm 128/256 bit security keys sck so si cs prog txdo rxdo txd1 rxd1 peripheral bus maxq30 32-bit cpu introduction bus jtag boot loader and ice debugger power monitor & reset control instruction memory boot rom packet memory crc32 timers (7) crc16 (2) vdd gnd gnd mult m plla plla1plla2 xtals xtal1a xtal2a div n div o plls2 xtala plla2 xtals plls2 xtala plla1 div p clk_afe div p max2992 shaper ifft fir notching max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 5 functional diagram device details downloaded from: http:///
max2992 lqfp top view p0.1/afe_sdin p0.3/afe_sclk v ss v ddc v ddio p0.0/afe_ cs 1 2 4 5 6 7 v ss p1.7/fsh_csp1.6/fsh_so p1.5/fsh_si p0.2/afe_sdout 3 p1.4/fsh_sckv ddio p1.3p1.2 p1.1/rxd0 p1.0/txd0 v ddc v ss xtal2s xtal1s prog tdo p3.0/txconv p3.1/txdata v ss v ddc p3.2/txclk v ddio p3.3/rxclk v ss v ddc p3.4/rxdata p3.5/rxconv p3.6/afe_ rst p3.7/ enrx p3.8/ entx v dd v ss 3029 28 27 26 25 24 23 22 21 20 19 18 17 31 32 5152 53 54 55 56 57 58 59 60 61 62 63 64 50 49 v ddc v ss p0.4/col p0.5/act p0.6/rdy p0.7/pulse rst v dd v ss xtal1atms tdi p2.0/sck p2.1/si xtal2a tckp2.2/agc_frz p2.3/so v ddio p2.4/afe_ shdn p2.5/ cs p2.6p2.7 v ddc v ss 8 9 10 11 12 13 14 15 16 48 47 45 44 43 42 46 41 40 39 38 37 36 35 34 33 max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 6 pin coniguration downloaded from: http:///
pin name type function 5, 9, 16, 19, 30, 33, 49, 53, 58 v ss p ground 6, 8, 20, 34, 54, 59, v ddc p +1.2v digital power supply. bypass v ddc to v ss with a 100nf capacitor as close as possible to the device. 7, 25, 39, 56 v ddio p +3.3v i/o power supply. bypass v ddio to v ss with a 100nf capacitor as close as possible to the device. 14 rst i/o reset. the rst input/output recognizes external active-low reset inputs and employs an internal pullup resistor to allow for a combination of wired-or external reset sources. bypass with a 220nf capacitor to v ss and use a 10k? pullup resistor to v ddio . 15, 50 v dd p +1.2v analog power supply. bypass v dd to v ss with a 100nf capacitor as close as possible to the device. 17 xtal1s i crystal oscillator input/output. the crystal oscillator input/output provide support for parallel resonant, at cut crystals. xtal1s also acts as an input when there is an external clock source in place of a crystal. xtal2s is the output of the crystal ampliier. signal xtals provides the clock base for the system clock. 18 xtal2s o 31 prog i prog . prog serves to initiate the uart boot loader. to activate the uart boot loader, prog must be held low for at least 3 system clock cycles. the host must then send the autobaud character (0x0d) at a baud rate of 57,600 baud or less. the max2992 detects the serial baud rate and reply with the prompt character (0x3e). at this time, the bootloader protocol can be used to program the device. 32 tdo o jtag data output 44 tdi i jtag data input 45 tms i jtag mode select input 46 tck i jtag clock input 47 xtal1a i crystal oscillator input/output. the crystal oscillator input/output provides support for parallel resonant, at cut crystals. xtal1a also acts as an input when there is an external clock source in place of a crystal. xtal2a is the output of the crystal ampliier. signal xtala provides the clock base for the afe interface. 48 xtal2a o port 0 1 p0.0/afe_ cs i/o o p0.0/afe_ cs . p0.0/afe_ cs is used by the max2992 g3-plc irmware to implement an spi command bus to the max2991 afe. p0.0/afe_ cs is the chip- select line to the max2991. this is the general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.0/afe_ cs provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 0, in/out a (note 1). max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 7 pin description downloaded from: http:///
pin name type function 2 p0.1/afe_sdin i/o o p0.1/afe_sdin. p0.1/afe_sdin is used by max2992 g3-plc irmware to implement an spi command bus to the max2991 afe. p0.1/afe_sdin is the serial data to the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.1/afe_sdin provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 0, in/out b (note 1). 3 p0.2/afe_sdout i/o o p0.2/afe_sdout. p0.2/afe_sdout is used by the max2992 g3-plc irmware to implement an spi command bus to the max2991 afe. p0.2/afe_sdout is the serial data returned from the max2991. this is the general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.2/afe_sdout provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 1, in/out a (note 1). 4 p0.3/afe_sclk i/o o p0.3/afe_sclk. p0.3/afe_sclk is used by max2992 g3-plc irmware to implement an spi command bus to the max2991 afe. p0.3/afe_sclk is the serial clock to the max2991.this is the general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.3/afe_sclk provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 1, in/out b (note 1). 10 p0.4/col i/o o p0.4/col. p0.4/col is used by the max2992 g3-plc irmware to indicate modem status. p0.4/col is the collision/packet error indicator, and can be used to drive a col led. this is the general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.4/col provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 2, in/out a (note 1). 11 p0.5/act i/o o p0.5/act. p0.5/act is used by the max2992 g3-plc irmware to indicate modem status. p0.5/act is the activity indicator and can be used to drive an act led. this is general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.5/act provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 2, in/out b (note 1). max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 8 pin description (continued) downloaded from: http:///
pin name type function 12 p0.6/rdy i/o p0.6/rdy. p0.6/rdy is used by the max2992 g3-plc irmware to indicate modem status. po.6/rdy is the modem-ready indicator and is used to drive a rdy led. this is the general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.6/rdy provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 3, in/out a (note 1). 13 p0.7/pulse i/o p0.7/ pulse . p0.7/ pulse is used by the max2992 g3-plc irmware to input pulses from an external zero-crossing detector. this is general-purpose i/o hardware and part of the 8-bit i/o port p0. p0.7/pulse provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. interrupt input/stop mode wake-up. timer i/o to timer 3, in/out b (note 1). port 1 21 p1.0/txd0 i/o o p1.0/txd0. p1.0/txd0 provides connections to dedicated uart hardware. this is used by the max2992 g3-plc irmware to implement the uart host interface. p1.0/ txd0 is the transmit data from the max2992 to the host. this is the general-purpose i/o hardware and part of the 8-bit i/o port p1. connect p1.0/txd0 with a 5k? resistor to v ddio (note 1). 22 p1.1/rxd0 i/o i p1.1/rxd0. p1.1/rxd0 provides connections to dedicated uart hardware. this is used by the max2992 g3-plc irmware to implement the uart host interface. p1.1/ rxd0 is the receive data from the host to the max2992. this is the general-purpose i/o hardware and part of the 8-bit i/o port p1 (note 1). 23 p1.2 i/o o p1.2. p1.2 provides connections to dedicated uart hardware used by the max2992 g3-plc irmware for reserved function. leave unconnected. this is the general- purpose i/o hardware and part of the 8-bit i/o port p1 (note 1). 24 p1.3 i/o i p1.3. p1.3 provides connections to dedicated uart hardware used by the max2992 g3-plc irmware for reserved function. this is the general-purpose i/o hardware and part of the 8-bit i/o port p1 (note 1). 26 p1.4/fsh_sck i/o o p1.4/fsh_sck. p1.4/fsh_sck provides dedicated connections to the spi hardware, and after power-on reset, the max2992 attempts to bootstrap code from an external lash if it is present. p1.4/fsh_sck is the serial clock from the max2992 to the lash. this is the general-purpose i/o hardware and part of the 8-bit i/o port p1. after boot, the spi hardware can be used by the max2992 g3-plc irmware. this is not utilized by the max2992 g3-plc irmware, but p1.4/fsh_sck provides the capability of: spi master clock output. spi slave clock input (note 1). max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 9 pin description (continued) downloaded from: http:///
pin name type function 27 p1.5/fsh_si i/o o p1.5/fsh_si. p1.5/fsh_si provides dedicated connections to the spi hardware, and after power-on reset, the max2992 attempts to bootstrap code from an external lash if it is present. p1.5/fsh_si is the serial data from the max2992 to the lash. this is the general-purpose i/o hardware and part of the 8-bit i/o port p1. after boot, the spi hardware can be used by the max2992 g3-plc irmware. this is not utilized by the max2992 g3-plc irmware, but p1.4/fsh_si provides the capability of: spi master output data. spi slave input data (note 1). 28 p1.6/fsh_so i/o o p1.6/fsh_so. p1.6/fsh_so provides dedicated connections to the spi hardware, and after power-on reset, the max2992 attempts to bootstrap code from an external lash if it is present. p1.6/fsh_so is the serial data return to the max2992 from the lash. this is the general-purpose i/o hardware and part of the 8-bit i/o port p1. after boot, the spi hardware can be used by the max2992 g3-plc irmware. this is not utilized by the max2992 g3-plc irmware, but p1.6/fsh_so provides the capability of: spi master data input. spi slave data output (note 1). 29 p1.7/fsh_cs i/o o p1.7/fsh_cs. p1.7/fsh_cs provides dedicated connections to the spi hardware, and after power-on reset, the max2992 attempts to bootstrap code from an external lash if it is present. p1.7/fsh_cs is the serial chip select from the max2992 to the lash. this is the general-purpose i/o hardware and part of the 8-bit i/o port p1. after boot, the spi hardware can be used by the max2992 g3-plc irmware. this is not utilized by the max2992 g3-plc irmware, but p1.7/fsh_cs provides the capability of: spi slave chip select (note 1). port 2 35 p2.7 i/o p2.7. p2.7 is not used by the max2992 g3-plc irmware. it is conigured as an unused input with the internal pullup enabled. it can be left unconnected. this is the general-purpose i/o hardware and part of the 8-bit i/o port p2. p2.7 provides hardware support that is available, but not utilized by the max2992 g3-plc irmware: hardware low control line cts for uart0. timer i/o to timer 4, in/out a. timer i/o to timer 6, in/out a (note 1). max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 10 pin description (continued) downloaded from: http:///
pin name type function 36 p2.6 i/o p2.6. p2.6 is not used by the max2992 g3-plc irmware. it is conigured as an unused input with the internal pullup enabled. it can be left unconnected. this is the general-purpose i/o hardware and part of the 8-bit i/o port p2. p2.6 provides hardware support that is available, but not utilized by the max2992 g3-plc irmware hardware low control line rts for uart0. timer i/o to timer 4, in/out a. timer i/o to timer 6, in/out a (note 1). 37 p2.5/ cs i/o o p2.5/ cs . p2.5/ cs provides dedicated connections to spi hardware. this is used by the max2992 g3-plc irmware to implement the spi host interface. p2.5/ cs is the active-low, chip select from the host to the max2992. this is general-purpose i/o hardware and part of the 8-bit i/o port p2. p2.5/ cs provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. timer i/o to timer 5, in/out b (note 1). 38 p2.4/afe_ shdn i/o p2.4/afe_ shdn . p2.4/afe_ shdn is used by the max2992 g3-plc irmware to place the max2991 afe into shutdown mode for lowest power consumption. p2.4/ afe_ shdn provides hardware support that is available, but not utilized by the max2992 g3-plc irmware. this is general-purpose i/o hardware and part of the 8-bit i/o port p2. timer i/o to timer 5, in/out a (note 1). 40 p2.3/so i/o o p2.3/so. p2.3/so provides dedicated connections to spi hardware. this is used by the max2992 g3-plc irmware to implement the spi host interface. p2.3/so is the serial data to the host from the max2992. this is general-purpose i/o hardware and part of the 8-bit i/o port p2 (note 1). 41 p2.2/agc_frz i/o o p2.2/agc_frz. p2.2/agc_frz provides dedicated connections to the phy hardware. this is used by the max2992 g3-plc irmware to signal the max2991 afe to freeze its automatic gain control (agc) setting. this is general-purpose i/o hardware and part of the 8-bit i/o port p2 (note 1). 42 p2.1/si i/o o p2.1/si. p2.1/si provides dedicated connections to spi hardware. this is used by the max2992 g3-plc irmware to implement the spi host interface. p2.1/si is the serial data from the host to the max2992. this is general-purpose i/o hardware and part of the 8-bit i/o port p2 (note 1). 43 p2.0/sck i/o i p2.0/sck. p2.0/sck provides dedicated connections to spi hardware. this is used by the max2992 g3-plc irmware to implement the spi host interface. p2.0/sck is the serial clock from the host to the max2992. this is general-purpose i/o hardware and part of the 8-bit i/o port p2 (note 1). max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 11 pin description (continued) downloaded from: http:///
pin name type function port 3 51 p3.0/txconv i/o o p3.0/txconv. p3.0/txconv provides dedicated connections to afe interface hardware. this is used by the max2992 g3-plc irmware to implement the afe interface to the max2991. p3.0/txconv is the tx enable line to the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 52 p3.1/txdata i/o o p3.1/txdata. p3.1/txdata provides dedicated connections to afe interface hardware. this is used by the max2992 g3-plc irmware to implement the afe interface to the max2991. p3.1/txdata is the tx serial data output to the max2991. this is general- purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 55 p3.2/txclk i/o o p3.2/txclk. p3.2/txclk provides dedicated connections to afe interface hardware. this is used by the max2992 g3-plc irmware to implement the afe interface to the max2991. p3.2/txclk is the tx serial clock to the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 57 p3.3/rxclk i/o o p3.3/rxclk. p3.3/rxclk provides dedicated connections to afe interface hardware. this is used by the max2992 g3-plc irmware to implement the afe interface to the max2991. p3.3/rxclk is the rx serial clock to the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 60 p3.4/rxdata i/o i p3.4/rxdata. p3.4/rxdata provides dedicated connections to afe interface hardware. this is used by the max2992 g3-plc irmware to implement the afe interface to the max2991. p3.4/afe_sdi is the rx serial data from the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 61 p3.5/rxconv i/o o p3.5/rxconv. p3.5/rxconv provides dedicated connections to afe interface hardware. this is used by the max2992 g3-plc irmware to implement the afe interface to the max2991. p3.5/rxconv is the rx enable line to the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 62 p3.6/afe_ rst i/o o p3.6/afe_ rst . p3.6/afe_ rst is used by the max2992 g3-plc irmware to reset the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 63 p3.7/ enrx i/o o p3.7/ enrx . p3.7/ enrx is used by the max2992 g3-plc irmware to enable the rx channel in the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). 64 p3.8/ entx i/o o p3.8/ entx . p3.8/ entx is used by the max2992 g3-plc irmware to enable the tx channel in the max2991. this is general-purpose i/o hardware and part of the 8-bit i/o port p3 (note 1). max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 12 pin description (continued) note 1: refer to the max2992 g3-plc firmware release note for updates to the function implemented. downloaded from: http:///
(t a = +25c, unless otherwise noted.) detailed description the max2992 integrates a high-performance maxim maxq30 32-bit risc core with optimized ofdm phy, 128/256-bit aes and crc hardware and peripherals including uart serial communication, spi interface, serial afe interface, watchdog/countdown timers, gpio, and external interrupts. the max2992 g3-plc modem is based on orthogonal frequency division multiplexing (ofdm) that places multiple evenly spaced carriers within the available frequency band. data is modulated onto these carriers and three modulation methods are support - ed: dbpsk, dqpsk, and d8psk. special data interleav - ing and forward error correction techniques enhance the robustness of communication that is immune to impulsive noise, adaptable to frequency selective channels, and robust in the presence of group delay. additional perfor - mance is obtained by adaptive tone mapping, a process by which the max2992 automatically detects carriers with poor snr, redistributing data onto better performing carri - ers. these features allow the max2992 to adapt to chan - nel conditions to provide superior data rates for a given channel condition. external flash stores the complete g3-plc application firmware supplied by maxim, which executes from the on-chip sram memory. g3-plc data and control is accomplished using the g3-plc modem interface over the uart or spi port. a full description of this interface is provided in the max2992 g3-plc interface guide . the mac, implemented on the maxq30, provides advanced csma/ca and arq functions and supports all common mac layer services. power management the max2992 power-management features minimize power consumption by clock gating and by adjusting the operating frequency. clock gating is used to eliminate active power of on-chip functional units when not in use. a clock divider of up to 256 is set by software to reduce the operating frequency to the required performance level per single application. normal operating mode in normal operating mode, the max2992s power- management features minimize power consumption by adjusting the frequency of cpu and phy operation to match the dynamic load on the device. idle mode in idle mode, the max2992 lowers power consumption by shutting down the maxq30 processor, but keeps the phys receive circuitry active so that it can detect a pow - erline packet. at least one clock must be running during idle mode. the processor awakes on the detection of a line sync at the beginning of a packet and returns to normal operating mode to receive the powerline packet. stop mode stop mode disables all clocks and circuits within the max2992. all modem functions are disabled. this is g3-plc data rate* fcc (150khz to 487.5khz) max2992 toc02 250 200 150 100 50 0 300 *point-to-point data rate (kbps) dbpsk (typ) dqpsk (typ) d8psk (typ) d8psk (max) robo (typ) g3-plc data rate* fcc (10khz to 487.5khz) max2992 toc03 250 200 150 100 50 0 300 *point-to-point data rate (kbps) dbpsk (typ) dqpsk (typ) d8psk (typ) d8psk (max) robo (typ) g3-plc data rate* cenelec a (36khz to 91khz) max2992 toc01 *point-to-point data rate (kbps) 40 30 20 10 dbpsk (typ) dqpsk (typ) d8psk (typ) d8psk (max) robo (typ) 0 50 max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 13 typical operating characteristics downloaded from: http:///
the lowest power state for the device where only leak - age power is consumed. an external interrupt causes the max2992 to exit from the stop mode. stop mode is controlled by the max2992 g3-plc firmware. refer to the max2992 g3-plc interface guide and max2992 g3-plc firmware release note for details on the use of stop mode.uart interface the max2992 features two hardware uarts (uart0 and uart1). uart0 has a 16-byte deep receive and transmit fifo with configurable interrupt thresholds and it supports hardware flow control. additionally, uart0 provides a hardware function for booting the device. the max2992 g3-plc firmware dedicates uart0 to the host interface with a baud rate of 115,200bps without flow con - trol. see the max2992 g3-plc firmware release note for additional information on the uart0 host interface settings. data transfer for communication on the power line and status and control commands are passed between host and the max2992 g3-plc modem over uart0. a simple frame format is used to define data and management primitives. a complete description of the frame format and command primitives is provided in the max2992 g3-plc interface guide . the max2992 g3-plc firmware utilizes uart1 for a reserved function. do not connect in user designs. serial peripheral interface (spi) the max2992 includes two serial peripheral interface modules (spi0 and spi1). the max2992 spi hard - ware can operate in slave or master modes. this is a common, high-speed, synchronous peripheral interface that shifts a bit stream of variable length and data rate between the microcontroller and other peripheral devices. programmable clock frequency, character lengths, polar - ity, and error handling enhance the usefulness of the peripheral. the maximum baud rate of the spi interface is half the system clock for master mode operation and 1/8th the system clock for slave mode operation. spi0 features a boot loading function that is the primary method for initializing the maxq30 memory after reset. spi0 boot loading is described in the boot options section. spi1 is assigned by the max2992 g3-plc firmware to implement an alternative host interface to uart0. when used as a host interface, four max2992 signals, p2.0/ sck, p2.5/ cs , p2.1/si, and p2.3/so must be connected to the host processor. refer to the max2992 g3-plc interface guide and max2992 g3-plc firmware release note for details on the use of the spi1 port.gpio the max2992 features 5v tolerant, 3.3v i/o. each i/o can be either an input or output. the max2992 g3-plc firmware configures each i/o as described in the pin configuration section. refer to the max2992 g3-plc firmware release note for additional gpio assignments. when in input mode, a weak pullup resistance is enabled pulling the i/o high. a series nfet provides the i/os high voltage tolerance ( figure 1 ). this degrades the voh observed and an external resistive pullup is recom - mended when the i/o is not actively driven (such as rst or prog , see the pin description ). timers the max2992 incorporates seven 16-bit programmable timers to allow precise control of internal and external events. each timer can operate in two modes: count-stop or wrap-round. the timers can be configured so that the timers generate interrupts upon reaching the extreme value. the timers also feature output modes suitable for synthesizing pwm. the max2992 g3-plc firmware uses these timers within its operating system, and to implement csma and ac phase detection. refer to the max2992 g3-plc interface guide and max2992 g3-plc firmware release note for information on timer use. clocks, pll, and power-on-resetthe max2992 provides two built-in oscillators each with an associated pll. the device can function in a one or a two crystal configuration, either reducing system compo - nents or maximizing flexibility of the operating frequencies in the system. the one crystal configuration requires a figure 1. gpio ren device weak pullup v ddio c load i/o max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 14 downloaded from: http:///
crystal connected between xtal1s and xtal2s. drive xtal1a low, have xtal2a unconnected, and connect v dd (pin 50) to v ss in one crystal mode. the max2992 g3-plc firmware uses the one crys - tal configuration with a 19.2mhz crystal connected to xtal1s and xtal2s. this crystal is used to generate both cpu and afe clocks. for this configuration, the cpu clock is set to 76.8mhz and afe clock is 6.4mhz for the cenelec frequency band with a 400khz sample rate. for fcc and arib bands, the afe clock is 19.2mhz with a 1.2mhz sample rate. the two crystal configuration requires that a crystal be connected between xtal1s and xtal2s, and xtal1a and xtal2a. refer to the max2992 g3-plc firmware release note for information on the crystal configuration used.external reset during normal operation, the max2992 can be placed into external reset mode by holding rst low for a mini - mum of eight clock cycles. after rst returns high, the maxq30 processor exits the reset state within eight clock cycles and begins program execution. watchdog timer the watchdog timer is a programmable hardware timer that can be used to reset the processor in case of a soft - ware lockup or other unrecoverable error. the max2992 g3-plc firmware uses the watchdog timer to enhance system reliability. afe serial interface the max2992 afe interface is designed to support the max2991. the interface includes separate receive and transmit serial interfaces. connect the max2992 to the max2991 as shown in figure 2 . refer to the max2991 data sheet for a description of the serial interface timing.boot options the max2992 executes program code from internal sram. this sram is volatile and must be loaded with application code after a power-cycle event. there are three options for loading the sram: automatic bootstrap from external flash bootstrap through the uart0 loader bootstrap through the jtag loader figure 3 shows the flow diagram for max2992 booting. the flowchart illustrates: at any time, the prog can be used to initiate a uart0 boot load cycle. from por, if the jtag interface and prog are not active, the max2992 boots load from external flash using the spi0 interface. once a program is loaded (by any means) and the program valid bit is set, successive resets causes reexecution of the loaded code. an additional boot load cycle is not required. automatic bootstrap from flash when the jtag and uart0 bootstrap are not select - ed, the max2992 boots from an external flash device over spi0. the flash must be preprogrammed with the max2992 g3-plc firmware. aes encryption of the flash image is supported to protect any deployed application. refer to the max2992 evaluation kit for details on programming the flash. bootstrap using the uart0 loader the max2992 can be booted over the uart0 host inter - face to avoid the need for a dedicated flash device. the uart0 boot load procedure is: 1. pull prog low for a minimum of 8 clock cycles. if automatic boot after power-up is desired, place an rc on prog so that prog rises at least 8 clock cycles after rst . 2. send the max2992 the character 0x0d (8-bit, no par - ity) at a rate of 57,600 baud or less. figure 2. max2992 to max2991 interface entx txdata txconv txclk enrx rxdata rxconv rxclk agc_cs reset p3.6afe_ rst p2.2/agc_frz p3.3/rxclk p3.5/rxconv p3.4/rxdata p3.7/ enrx p3.2/ txclk p3.0/ txconv p3.1/txdata p3.8/ entx afe max2991 max2992 max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 15 downloaded from: http:///
3. the max2992 measures the timing and autocalibrates to the baud rate. 4. the max2992 acknowledges entry to the serial loader by transmitting a prompt character (0x3e). details of using the serial boot-loader commands to imple - ment a uart0 bootstrap are provided in the max2992 evaluation kit. the serial bootloader does not utilize the hardware flow control feature of uart0. the loader man - ages flow control using the communication protocol. toggling rst exits the serial boot loader whereby the max2992 follows the boot sequence described by figure 3 . details of using the serial boot loader commands to imple - ment a uart0 boot strap are provided in the max2992 evaluation kit. figure 3. max2992 boot sequence flow chart spe? reset reset prog input execute rom 0x800000h bootstrap from flash uart0 autobaud uart0 bootloader yes pspe? yes nono pv? pass yes no set pv yes reset no set pv on successful code load set pspe jtag bootloader run application jump to 0x000000h spe = system program enable bit within the jtag spr register. pspe = prog system program enable bit, set by the prog input and cleared by other forms of reset. pv = program valid bit, set at the completion of loading code into instruction ram and cleared by power-on reset. max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 16 downloaded from: http:///
bootstrap using the jtag loader the jtag bootstrap loader mode initializes the nonvola - tile memory of the internal maxq30 microcontroller. the jtag loader is used by maxim as a development inter - face and should not be utilized in user systems. ac phase detector to know the phases of each meter, the max2992 fea - tures internal timers to measure time intervals of pulses resulted from zero-crossing of ac 50hz/60hz as shown in figure 4 . p0.7/pulse is used to input pulses received from an external zero-crossing detector to reset an 8-bit counter. the minimum required pulse width is 1% of the cycle. csma/ca concurrent transmission by multiple nodes can result in frame collisions that occur when multiple transmissions interfere with each other, distorting the signal sufficiently to cause communication to fail. carrier sense multiple access/collision avoidance (csma/ca) is a mechanism to reduce the probability of collisions. when using csma as soon as a node is ready to transmit a packet, the device checks the channel for activity. if no other node is transmitting the node transmits its packet. if another transmitter is detected, the device waits for that transmis - sion to end and then waits for a randomly selected period of time for another device to start transmitting on the channel. this wait time is called a random back-off time. if no other device has started transmitting at the end of the back-off time, the device starts its transmission. this process is repeated until the device gets access to the channel. all the devices in the system randomly choose their back-off time from one of a limited number of pre - defined time slots after the end of the prior transmission. automatic repeat request (arq) to enhance error detection and improve data reliability, the max2992 utilizes an automatic repeat request proto - col. since plc communication is a half-duplex connec - tion, the transmitter waits for an acknowledgment (ack) of each transmission before it proceeds with the next transmission. if the transmitter does not receive an ack packet, the transmitter resends the packet. phy overview the max2992 powerline modem is designed to over - come the challenges associated with the harsh powerline environment for data communications. some of the chal - lenges are noted below: channel variability with frequency, location, and time narrowband, wideband, and impulsive noise com - monly present on the power line presence of narrowband interference and multipath signal propagation low and time varying network impedance (3 to 30 ) propagation through transformers that subject the channel to severe group delay and attenuation the max2992 modem solution is based on orthogonal frequency division multiplexing (ofdm) to overcome the powerline channel impairment, providing high reliability in data transmission. this method combines good band - width efficiency (high data rate) with the possibility of a very flexible bandwidth allocation. in combination with error correction coding, the max2992 is robust in the presence of frequency selective channels and resilient to jammer signals and impulsive noise. figure 4. zero-crossing ac detector pulse width half cycle =10ms/8.3ms zero-crossing detector 50hz/60hz max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 17 downloaded from: http:///
the ofdm technique places evenly spaced carriers into the available frequency band. the max2992 can be con - figured to operate in a subset of frequencies in the range 10khz to 490khz, encompassing cenelec, arib, and fcc frequency bands. three modulation methods are supported; dbpsk, dqpsk, and d8psk. this allows the max2992 to trade off channel condition and data rate to achieve the highest possible data through for a given channel condition. additional performance is obtained by adaptive tone mapping, a process by which the max2992 automatically detects carriers with poor snr, redistribut - ing data onto better performing channels. there are several advantages of the max2992 ofdm scheme as compared to traditional single carrier fsk or spread-spectrum systems: the max2992 ofdm allows an extremely flexible allocation and use of a given channel bandwidth. as an example, the lower and the upper limit of the used frequency band can easily be configured. it is also possible to use two or more noncontiguous sub-bands for the transmission of a single data stream. it is considerably more robust against intersymbol inter - ference (isi) or group delay distortion caused by the transmission channel than narrowband systems. this is mainly due to the fact that the parallel transmission on several carriers leads to longer symbol duration. furthermore, isi is simply removed by inserting guard intervals and cyclic prefixes between the symbols. the max2992 is robust in presence of narrowband inter - ference because such jammers typically destroy a single carrier only. through the use of forward error correction codingthe erroneous data is detected and corrected using the received coded information. on the transmitter side, the plc modem layer receives input data from the uart and passes the data through the fec, modulator, and ifft. on the receiver side, the plc modem layer receives inputs from the afe and hands the data over to the application layer ( figure 5 ). two separate signal paths are shown for the receiver. the first path is dedicated to the detection of narrow band interference, and the second path processes the preamble for symbol and frame synchronization followed by the fec decoding block. after descrambling the output of the fec decoder data are available for the mac layer. table 1 shows the frequency bands with which the max2992 modem complies. the combined phy and mac in the max2992 meet the transmitter/receiver technical requirements for highly reliable data communication in powerline networks, as shown in table 2 and table 3 . table 1. frequency bands supported by the max2992 table 2. frame error rate requirements in awgn channels (100 bytes) table 3. receiver specification with max2991 component number of carriers first carrier (khz) last carrier (khz) cenelec a 36 35.93 90.62 cenelec b 16 98.43 121.87 cenelec c 7 128.12 137.50 cenelec bc 26 98.43 137.50 cenelec d 4 142.18 146.87 fcc1 72 154.6875 487.5 fcc2 97 37.5 487.5 fcc3 24 154.6875 262.5 fcc4 40 304.6875 487.5 arib1 54 154.6875 403.125 arib2 79 37.5 403.125 signal-to- noise ratio (db) modulation and coding rate frame error rate (%) -1.2 robo 0.01 2.6 dbpsk 0.01 6.1 dqpsk 0.01 9.9 d8psk 0.01 receiver specification requirement sensitivity 1mv dynamic range 60db clock frequency tolerance 25ppm max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 18 downloaded from: http:///
figure 5. transmitter/receiver block diagram of the baseband processor mapping dbpsk dqpsk d8psk jammer canceller preemphasis ifft add cp windowing demodulator dbpsk dqpsk d8psk interleaver convolutional encoder ofdm modulator fec encoder power line ofdm demodulator fec decoder reed-solomon encoder scrambler descrambler reed-solomon decoder detected not detected bit afe robust (rc4) viterbi decoder robust4 and robust combiner deinterleaver jammer detector rms measurement sync detection remove cp fft fch data fch data s-robust (rc6) afe channel estimation max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 19 downloaded from: http:///
v ddio to v ss ....................................................... -0.5v to +4.0v v ddc to v ss ........................................................ -0.5v to +1.5v v dd to v ss ........................................................... -0.5v to +1.5v xtal1a, xtal2a, xtal1s, xtal2s to v ss ....... -0.5v to +4.0v all i/o pins ............................................................ -0.5v to +5.5v continuous power dissipation (t a = +70c) lqfp (derate 25mw/c above +70c) ..................... 2000mw operating temperature range ......................... -40c to +105c junction temperature ...................................................... +125c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c lqfp junction-to-ambient thermal resistance ( ja ) .......... 40c/w junction-to-case thermal resistance ( jc ) ................. 8c/w (note 2) (v ddio = +3.3v, v ddc = v dd = +1.2v, v ss = 0, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units power-supply characteristics digital supply voltage range v ddio 3.0 3.3 3.6 v core supply voltage range v ddc 1.14 1.2 1.32 v pll supply voltage range v dd pins 15 and 50 1.14 1.2 1.32 v operating supply current i operating v ddio supply current 25 ma v ddc supply current 40 70 v dd supply current 1 3 idle mode current i idle v ddio supply current 25 ma v ddc supply current 12 v dd supply current 1 stop mode current i stop v ddio supply current 2 ma v ddc supply current 1.8 v dd supply current 0.2 output voltage high v oh i oh = -5ma 2.4 v i oh = -8ma (pins 55 and 57) 2.4 output voltage low v ol i ol = 5ma 0.4 v i ol = 8ma (pins 55 and 57) 0.4 logic input characteristics input high voltage v ih 2 5.5 v xtal1s, xtal1a 2 3.6 input low voltage v il -0.3 +0.8 v input capacitance c in xtal1s and xtal1a 3 pf input leakage current i in internal pullup disabled -10 +10 a gpio pullup resistance r pu internal pullup enabled 25 45 60 k? max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 20 note 2: package thermal resistances were obtained using the method described in jedec specification jesd51- 7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristicselectrical characteristics downloaded from: http:///
(v ddio = +3.3v, v ddc = v dd = +1.2v, v ss = 0, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units external crystal/input frequency 1/t xtal esr < 90? for 19.2mhz (note 4) 2 19.2 30 mhz external crystal/clock tolerance (note 4) 25 ppm cpu clock frequency 1/t cpu as conigured by g3-plc irmware (note 4) 76.8 mhz afe clock frequency 1/t afe as conigured by g3-plc irmware (note 4) 48 mhz uart baud rate as conigured by g3-plc irmware (notes 3 and 4) 115,200 1/16 x t cpu bps spi master (flash bootloader, see figure 6) spi master operating frequency 1/t mck flash boot after por (note 4) 1/2 x t xtal mhz user programmable after bootstrap (note 4) 1/ 2 x t cpu i/o rise/fall time t mrf c l = 100pf, pullup = 560? 5 ns sclk output pulse width high/low t mch , t mcl t mck /2 - t rf ns mosi output valid to sclk sample edge t moh mosi setup t mck /2 - t rf ns mosi output hold after sclk last sample edge t mov t mck /2 - t rf ns sclk last sample edge to mosi output change t mlh mosi last hold t mck + t rf ns miso input valid to sclk sample edge t mis miso setup 10 ns miso input hold after sclk sample edge t mih 0 ns spi slave (see figure 7) spi slave operating frequency 1/t sck (note 4) 1/8 x t cpu mhz i/o rise/fall time t srf c l = 100pf, pullup = 560? 5 ns sclk input pulse width high/low t sch , t scl t cpu ns ssel active to first shift edge t sse 0 ns mosi input to sclk sample edge rise/fall setup t sis t cpu ns max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 21 ac electrical characteristics downloaded from: http:///
(v ddio = +3.3v, v ddc = v dd = +1.2v, v ss = 0, t a = -40c to +105c, unless otherwise noted. typical values are at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization.) note 3: typical values are measured at t a = +25c, v ddc = 1.2v. note 4: guaranteed by design. note 5: the maximum operating frequency is 20mhz when paired with the max2991. parameter symbol conditions min typ max units mosi input from sclk sample edge transition hold t sih t cpu ns miso output valid after sclk shift edge transition t sov 4 x t cpu ns ssel inactive to next ssel asserted t ssh 2 x t cpu ns sclk inactive to ssel deasserted t sd 3 x t cpu ns miso output disabled after ssel edge deasserted t slh 4 x t cpu ns afe interface serial mode (see figure 8) afe interface operating frequency 1/t trck (note 5) 48 mhz clock rise/fall time t crf c l = 100pf 5 ns rxclk/txclk output pulse width high/low t rch , t rcl 0.4 x t trck 0.6 x t trck ns sdi input setup to rxclk active edge t ris 6 ns sdi input hold after rxclk active edge t rih 1 ns rxen/txen inactive level output pulse width t trew 0.8 x t trck t trck 1.2 x t trck ns rxclk/txclk to rxen/txen active t tredf 0 10 ns rxclk/txclk to rxen/txen inactive t tredr 0 10 ns txclk to sdo output t tod 0 10 ns max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 22 ac electrical characteristics (continued) downloaded from: http:///
figure 6. spi master timing diagram figure 7. spi slave timing diagram mosimiso shift sample shift sample ssel (sas = 0) sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 t mck t mch t mov t moh t mcl t rf t mis t mih t mlh msb msb lsb lsb msb-1 msb-1 shift sample shift sample ssel sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 mosi moso t sck t sd t sse t ssh t sch t sis t sih t scl t sov t slh t rf msb lsb msb-1 msb msb-1 lsb max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 23 downloaded from: http:///
applications information the max2992 is a powerline communications device that transports information from the application layer across a powerline network. in a typical application, the max2992 is used with an external host processor that handles application layers and an ipv6 stack. for instance, in a metering application, an external host processor that is connected to the max2992 using the uart or spi interface processes metering data and encapsulates the processed data into ipv6 packets to be transported over the ac line. additionally, the host implements inter - face primitives to communicate to the max2992. these primitives direct data transfer as well as status and control commands between the host and the max2992. refer to the max2992 g3-plc interface guide for a description of the interface primitives. external crystal requirements the max2992 accepts crystals of various designs to set the clock frequency. for example, use a crystal with a maximum esr of 1k and c l of 20pf between 2mhz and 6mhz. use a crystal with a maximum esr of 160 and c l of 16pf between 6mhz and 10mhz. use a crystal with a maximum esr of 90 and c l of 12pf between 10mhz and 20mhz. use a crystal with a maximum esr of 40 and c l of 8pf between 20mhz and 30mhz. external flash requirements an external flash device is required for the automatic bootstrap from the external flash option (see the boot options section). the external flash supported by the max2992 for booting is the at45db021d. figure 8. afe timing diagram t trew t trew t rch t rcl t tredf t tod t tredf t ris t rih t tredr t tredr txconv txclk txdata rxconv rxclk rxdata t rch t rcl max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 24 downloaded from: http:///
network support depending on the application requirements, the max2992 can use various network topologies. in a star topology, communication is established between devices and a single central controller. applications such as industrial control and monitoring, sensor networks, asset and inven - tory tracking, and security benefit from the star topology. the max2992 can also operate in a tree network topol - ogy where a controller communicates with devices in the network either directly or by having messages forwarded by other devices in the network. applications such as metering and lighting automation benefits from the tree network topology. the max2992 supports peer-to-peer mesh network topologies. in peer-to-peer mesh networks, two devices communicate with each other using other devices as for - warders without either of the devices in the network being a controller. max2992 routing the max2992 network of devices discovers routes among the devices in the network. a route is discovered by a device sending a route request message. the route request message is sent by a device when the device does not know how to route its message to the desired device. every device in the network except the target device forwards the route request message at least once. when a device receives a route request message, it cal - culates the route cost required for the message to get to it. it stores that route cost and sends on the route request message with the route cost it calculated. since there are many devices forwarding the route request message, devices are likely to receive more than one route request messages to support the creation of the same route. the redundant copies of the message have the same or higher calculated route cost. all the redundant copies are dropped. when the message forwarding is complete, the devices along the best path have the lowest route cost back to the route request originator in their memory. figure 12 shows the route generated in bold by the route request that makes up the best path from the requester to the target. the lighter lines show messages that are not on the optimal path. figure 9. star network topology figure 11. peer-to-peer network topology figure 10. tree network topology max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 25 downloaded from: http:///
when the route request message reaches the target device, it broadcasts a route reply message. this mes - sage includes the lowest route cost from the requestor it received. other devices update the message and rebroadcast it if the route reply message contains a route cost from the requester that is more than the route cost back to the requester in their memory. each device updates its routing table with the path that is the lowest route cost from the target. figure 13 shows the route reply messages generated in this example. the max2992 builds an optimal route from device a to device b. figure 12. route request message flow figure 13. route reply message flow a b a b max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 26 downloaded from: http:///
+ denotes lead(pb)-free/rohs-compliant package. t = tape and reel. part temp range pin-package max2992ecb+t -40c to +85c 64 lqfp max2992gcb+ -40c to +85c 64 lqfp max2992gcb+t -40c to +85c 64 lqfp package type package code outline no. land pattern no. 64 lqpf c64-8 21-0083 90-0141 max2992 g3-plc mac/phy powerline transceiver www.maximintegrated.com maxim integrated 27 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos ordering information (continued) downloaded from: http:///
revision number revision date description pages changed 0 3/11 initial release 1 4/14 updated general description , beneits and features , ordering information , pin description , electrical characteristics table, ac electrical characteristics table sections and table 1 1, 11, 18, 20, 21 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max2992 g3-plc mac/phy powerline transceiver ? 2014 maxim integrated products, inc. 28 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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